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WM8728 24-bit, 192khz stereo dac with volume control anddsd support wolfson microelectronics plc w :: www.wolfsonmicro.com production data, december 2002, rev 3.1 copyright ? 2002 wolfson microelectronics plc description the WM8728 is a high performance stereo dac designed for audio applications such as dvd, home theatre systems, and digital tv. the WM8728 supports pcm data input word lengths from 16 to 32-bits and sampling rates up to 192khz. alternatively the WM8728 can operate in dsd compatible mode where a 64x bitstream is input for each channel. the WM8728 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo dac in a small 20-pin ssop package. the WM8728 also includes a digitally controllable mute and attenuate function for eachchannel. the WM8728 supports a variety of connection schemes for audio dac control. the 2 or 3-wire mpu serial port provides access to a wide range of features including on-chip mute, attenuation and phase reversal. a hardware controllable interface is also available (dsd operation is only possible in hardware mode). the WM8728 is an ideal device to interface to ac-3 , dts , and mpeg audio decoders for surround sound applications, or for use in dvd players supporting dvd-a. features ? stereo dac with24 bit pcm or single bit dsd operation ? audio performance - 106db snr (a weighted @ 48khz) dac - -97db thd ? dac sampling frequency: 8khz - 192khz ? 2 or 3-wire serial control interface or hardware control ? programmable audio data interface modes - i 2 s, left, right justified, dsp - 16/20/24/32 bit word lengths ? independent digital volume control on eachchannel with 127.5db range in 0.5db steps ? 3.0v - 5.5v supply operation ? 20-pin ssop package ? exceeds dolby class a performance requirements applications ? dvd-audio and dvd universal players ? home theatre systems ? digital tv ? digital broadcast receivers block diagram serial interface mute/ atten control interface bckin sigma delta modulator lrcin din mute/ atten sigma delta modulator digital filters mclk dvdd avdd muteb sdidem sckdsd lati2s mode csbiwl zero voutl voutr vmid agnd dgnd low pass filter low pass filter right dac left dac mux mux pcm/dsd WM8728 vrefp vrefn w
WM8728 production data w pd rev 3.1 december 2002 2 pin configuration ordering information device temp. range package WM8728eds -25 to +85 o c 20-pin ssop WM8728eds/r -25 to +85 o c 20-pin ssop (tape and reel) muteb csbiwl vrefp m o d e l a t i 2 s dgnd bckin lrcin voutl vmid vrefn agnd WM8728 16 15 14 20 19 18 17 5 6 7 1 2 3 4 dvdd zero mclk din 13 12 11 8 9 10 avdd voutr sdidem sckdsd note: reel quantity = 2,000 pin description pin name type description 1 lrcin digital input dac sample rate clock input: pcm input mode right channel dsd bitstream input: dsd input mode 2 din digital input serial audio data input: pcm input mode left channel dsd bitstream input: dsd input mode 3 bckin digital input audio data bit clock input 4 mclk digital input master clock input 5 zero digital output (open drain) infinite zero detect flag (l = idz detected, h = idz not detected). 6 dgnd supply digital ground supply 7 dvdd supply digital positive supply 8 voutr analogue output right channel dac output 9 agnd supply analogue ground supply 10 avdd supply analogue positive supply 11 voutl analogue output left channel dac output 12 vmid analogue output mid rail decoupling point 13 vrefn supply dac negative reference C normally agnd, must not be below agnd 14 vrefp supply dac positive reference C normally avdd, must not be above avdd 15 csbiwl digital input (pull-up) software mode: 3-wire serial control chip select hardware mode: input word length 16 mode digital input (pull-down) control mode selection (l = hardware, h = software) 17 muteb digital bi-directional mute control (l = mute on, h = mute off, z = automute enabled) 18 sdidem digital bi-directional software mode: 3 or 2-wire serial control data input: hardware mode: de-emphasis select 19 sckdsd digital input (pull-down) software mode: 3 or 2-wire serial control clock input hardware mode: dsd bitstream operation select 20 lati2s digital input (pull-up) software mode 3-wire serial control load input hardware mode: input data format selection note: digital input pins have schmitt trigger input buffers.
WM8728 production data w pd rev 3.1 december 2002 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. the WM8728 has been classified as msl1, which has an unlimited floor life at <30 o c / 85% relative humidity and therefore will not be supplied in moisture barrier bags. condition min max digital supply voltage -0.3v +7v analogue supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 50mhz operating temperature range, t a -25 c+85 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c package body temperature (soldering 10 seconds) +260 c package body temperature (soldering 2 minutes) +183 c note: analogue and digital grounds must always be within 0.3v of each other.
WM8728 production data w pd rev 3.1 december 2002 4 dc electrical characteristics parameter symbol test conditions min typ max unit digital supply range dvdd 3.0 5.5 v analogue supply range avdd 3.0 5.5 v ground agnd, dgnd 0 v difference dgnd to agnd -0.3 0 +0.3 v analogue supply current avdd = 5v 19 ma digital supply current dvdd = 5v 8 ma analogue supply current avdd = 3.3v 18 ma digital supply current dvdd = 3.3v 4 ma note: dvdd supply needs to be active before avdd supply for correct device power on reset. see power supply timing section. electrical characteristics test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2.0 v output low v ol i ol = 1ma dgnd + 0.3v v output high v oh i oh = 1ma dvdd C 0.3v v analogue reference levels reference voltage vmid (vrefp - vrefn)/2 - 50mv (vrefp - vrefn)/2 (vrefp - vrefn)/2 + 50mv v potential divider resistance r vmid 10k ohms dac output (load= 10k ohms. 50pf) 0dbfs full scale output voltage at dac outputs 1.1 x avdd/5 vrms snr (note 1,2,3) a-weighted, @ fs = 48khz 100 106 db snr (note 1,2,3) a-weighted @ fs = 96khz 106 db snr (note 1,2,3) a-weighted @ fs = 192khz 106 db snr (note 1,2,3) a-weighted, @ fs = 48khz avdd, dvdd = 3.3v 102 db snr (note 1,2,3) a-weighted @ fs = 96khz avdd, dvdd = 3.3v 102 db snr (note 1,2,3) nonaweighted@fs = 48khz 103 db thd (note 1,2,3) 1khz, 0dbfs -97 db thd+n (dynamic range, note 2) 1khz, -60dbfs 100 106 db dac channel separation 100 db
WM8728 production data w pd rev 3.1 december 2002 5 test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit analogue output levels load = 10k ohms, 0dbfs 1.1 v rms output level load = 10k ohms, 0dbfs, (avdd = 3.3v) 0.726 v rms gain mismatch channel-to-channel 1 %fsr to midrail or a.c. coupled 1kohms minimum resistance load to midrail or a.c. coupled (avdd = 3.3v) 600 ohms maximum capacitance load 5v or 3.3v 100 pf output d.c. level (vrefp - vrefn)/2 v power on reset (por) por threshold 2.4 v notes: 1. ratio of output level with1khz full scale input, to the output level withall zeros into the digital input, over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with10uf and 0.1uf capacitors (smaller values may result in reduced performance). terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full-scale output and the output with a zero signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full-scale signal down one channel and measuring the other.
WM8728 production data w pd rev 3.1 december 2002 6 master clock timing mclk t mclkl t mclkh t mclky figure 1 master clock timing requirements test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit master clock timing information mclk master clock pulse widthhigh t mclkh 13 ns mclk master clock pulse widthlow t mclkl 13 ns mclk master clock cycle time t mclky 26 ns mclk duty cycle 40:60 60:40 digital audio interface bckin lrcin t bch t bcl t bcy din t lrsu t ds t lrh t dh figure 2 digital audio data timing test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 40 ns bckin pulse widthhigh t bch 16 ns bckin pulse widthlow t bcl 16 ns lrcinset-uptimeto bckin rising edge t lrsu 8ns lrcin hold time from bckin rising edge t lrh 8ns dinset-uptimetobckin rising edge t ds 8ns dinholdtimefrombckin rising edge t dh 8ns
WM8728 production data w pd rev 3.1 december 2002 7 dsd audio monophase interface mclk t bch t bcl t bcy din/lrcin t ds t dh figure 3 normal dsd timing requirements test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information mclk cycle time t bcy 344 ns mclk pulse widthhigh t bch 160 ns mclk pulse widthlow t bcl 160 ns din/lrcin set-up time to mclk rising edge t ds 10 ns din/lrcin hold time from mclk rising edge t dh 10 ns power supply timing dvdd avdd t psu figure 4 power supply timing requirements test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit power supply input timing information dvddsetuptimetoavdd rising edge t psu measured from dvdd/2 to avdd/2 10 ms
WM8728 production data w pd rev 3.1 december 2002 8 dsd audio biphase interface mclk din/lrcin d0 d1 d1 d2 d2 t bcy t bch t bcl t ph t su t hd t mcl t mch t mcy bckin figure 5 biphase dsd timing requirements test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 162.8 ns bckin pulse widthhigh t bch 80 81.4 ns bckin pulse widthlow t bcl 80 81.4 ns mclk cycle time t mcy 325.5 ns mclk pulse widthhigh t mch 160 162.8 ns mclk pulse widthlow t mcl 160 162.8 ns phase shift between bckin and mclk t ph 20 ns datasetuptimetobckin falling edge t su 10 ns dataholdtimetobckin rising edge t hd 10 ns
WM8728 production data w pd rev 3.1 december 2002 9 mpu 3-wire interface timing lati2s sckdsd sdidem t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css csbiwl t cssh t cssu figure 6 program register input timing - 3-wire serial control mode test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sckdsd rising edge to lati2s rising edge t scs 40 ns sckdsd pulse cycle time t scy 80 ns sckdsd pulse widthlow t scl 20 ns sckdsd pulse widthhigh t sch 20 ns sdidem to sckdsd set-up time t dsu 20 ns sckdsd to sdidem hold time t dho 20 ns lati2s pulse widthlow t csl 20 ns lati2s pulse widthhigh t csh 20 ns lati2s rising to sckdsd rising t css 20 ns csbiwl to lati2s set-up time t cssu 20 ns lati2s to csbiwl hold time t cssh 20 ns
WM8728 production data w pd rev 3.1 december 2002 10 mpu 2-wire interface timing sckdsd sdidem t ssu t shd t scy t sch t scl t dsu t dhd t scr t scf t df t dr t esu figure 7 program register input timing - 2-wire serial control mode test conditions avdd, dvdd = 5v, agnd = 0v, dgnd = 0v, t a =+25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sckdsd pulse cycle time t scy 80 ns sckdsd pulse widthlow t scl 20 ns sckdsd pulse widthhigh t sch 20 ns sdidem to sckdsd data set- up time for start signal t ssu 10 ns sdidem from sckdsd data hold time for start signal t shd 10 ns sdidem to sckdsd data set- up time t dsu 20 ns sckdsd to sdidem data hold time t dhd 20 ns sckdsd rise time t scr 5ns sckdsd fall time t scf 5ns sdidem rise time t dr 5ns sdidem fall time t df 5ns sdidem to sckdsd data set- up time for stop signal t esu 10 ns notes: 1. the address for the device in the 2-wire mode is 001101x (binary) with the last bit selectable. 2. in the two-wire interface mode, the csbiwl pin indicates the final bit of the chip address. 3. in 2-wire mode the lati2s pin should be tied to either dgnd or dvss to avoid noise toggling the interface into 3-wire mode.
WM8728 production data w pd rev 3.1 december 2002 11 device description introduction the WM8728 is a high performance dac designed for digital consumer audio applications. its range of features makes it ideally suited for use in dvd players, av receivers and other high-end consumer audio equipment. WM8728 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo dac and output smoothing filters. the WM8728 includes an on-chip digital volume control, configurable digital audio interface and a 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. control of internal functionality of the device is by either hardware control (pin programmed) or software control (2 or 3-wire serial control interface). the mode pin selects between hardware and software control. the software control interface may be asynchronous to the audio data interface. in which case control data will be re-synchronised to the audio processing internally. operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled in hardware mode, or serial controlled when in software mode. sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate master clock is input. support is also provided for up to 192ks/s using a master clock of 128fs or 192fs. the audio data interface supports right justified, left justified and i 2 s (philips left justified, one bit delayed) interface formats along with a highly flexible dsp serial port interface. when in hardware mode, the three serial interface pins become control pins to allow selection of, input data format type (i 2 s or right justified), input word length (20 or 24 bit) and de-emphasis functions. in dsd mode, a separate bitstream data input pin is required for each of the channels, plus a 64fs dataclock mclk. these signals are applied via pins din and lrcin and the signals routed internally into the dac circuits, under control of the sckdsd mode select pin (19) see figure 3. additionally a phase modulation scheme is supported, whereby the audio data is transmitted as a manchester encoded bitstream. this has the advantage of removing the significant spectral audio energy from the datastream, minimising digital signal corruption of the analogue outputs. in order to simplify decoding of this phase modulated data, a 2x speed clock (bckin) is used to sample the incoming data. see figure 5. the device is packaged in a small 20-pin ssop. clocking schemes in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio systems master clock. the external master system clock can be applied directly through the mclk input pin withno software configuration necessary for sample rate selection. note that on the WM8728, mclk is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. WM8728 always acts as a slave and requires clocks to be inputs.
WM8728 production data w pd rev 3.1 december 2002 12 digital audio interface audio data is applied to the internal dac filters via the digital audio interface. five popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp early mode ? dsp late mode all five formats send the msb first and support word lengths of 16, 20, 24 and 32 bits with the exception that 32 bit data is not supported in right justified mode. din and lrcin maybe configured to be sampled on the rising or falling edge of bckin. in left justified, right justified and i 2 s modes, the digital audio interface receives data on the din input. audio data is time multiplexed with lrcin indicating whether the left or right channel is present. lrcin is also used as a timing reference to indicate the beginning or end of the data words. the minimum number of bckins per lrcin period is 2 times the selected word length. lrcin must be high for a minimum of word length bckins and low for a minimum of word length bckins. any mark to space ratio on lrcin is acceptable provided the above requirements are met the WM8728 will automatically detect when data with a lrcin period of exactly 32 bckins is sent, and select 16-bit mode - overriding any previously programmed word length. word length will revert to a programmed value only if a lrcin period other than 32 bckins is detected. in dsp early or dsp late mode, the data is time multiplexed onto din. lrcin is used as a frame sync signal to identify the msb of the first word. the minimum number of bckins per lrcin period is 2 times the selected word length. any mark to space ratio is acceptable on lrcin provided the rising edge is correctly positioned. (see figure 11 and figure 12) left justified mode in left justified mode, the msb is sampled on the first rising edge of bckin following a lrcin transition. lrcin is high during the left data word and low during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 8 left justifiedmode timing diagram
WM8728 production data w pd rev 3.1 december 2002 13 right justified mode in right justified mode, the lsb is sampled on the rising edge of bckin preceding a lrcin transition. lrcin is high during the left data word and low during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 9 right justifiedmode timing diagram i 2 smode in i 2 s mode, the msb is sampled on the second rising edge of bckin following a lrcin transition. lrcin is low during the left data word and high during the right data word. left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1bckin 1bckin figure 10 i 2 s mode timing diagram dsp early mode in dsp early mode, the first bit is sampled on the bckin rising edge following the one that detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length(iwl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1bckin 1bckin figure 11 dsp early mode timing diagram
WM8728 production data w pd rev 3.1 december 2002 14 dsplatemode in dsp late mode, the first bit is sampled on the bckin rising edge, which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. lrcin bckin din input word length(iwl) 1/fs left channel n 2 1 n-1 lsb msb n 2 1 n-1 right channel no valid data 1 figure 12 dsp late mode timing diagram audio data sampling rates the master clock for WM8728 can range from 128fs to 768fs, where fs is the audio sampling frequency (lrcin) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the WM8728 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). if there is a greater than 32 clocks error, the interface shuts down the dac and mutes the output. the master clock should be synchronised with lrcin, although the WM8728 is tolerant of phase differences or jitter on this clock. see table 1 master clock frequency (mhz) (mclk) sampling rate (lrcin) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.114 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable table 1 typical relationships between master clock frequency andsampling rate
WM8728 production data w pd rev 3.1 december 2002 15 hardware dsd mode dsd mode is selected by taking the sckdsd pin high whilst the mode pin is low. in this mode the internal digital filters are bypassed, and the already modulated bitstream data is applied directly to the switched capacitor dac filter where it is converted and lowpass filtered, see figure 27 to figure 30. two formats are supported for data transfer, monophase or biphase modulated. in monophase mode, dsd data is simply clocked into the device using the rising edge of the 64fs mclk signal. in biphase mode, the data is supplied in manchester encoded form (a bit transition occurs during every data bit, which shapes the spectral energy minimising corruption of the analogue outputs). a secondary clock bckin, at 128fs is used to simplify data recovery, the data simply being clocked with the falling edge of bckin when mclk is at logic low (0v). see figure 3 and figure 5 for details of dsd interface timing. hardware control modes when the mode pin is held low, the following hardware modes of operation are available. mute and automute operation in both hardware and software modes, pin 17 (muteb) controls the selection of mute directly, and can be used to enable and disable the automute function. automute is enabled by leaving muteb pin floating, it is disabled by applying a signal to the pin. when left floating this pin becomes an output and indicates infinite zero detect (izd), see also pin 5 (zero). the status of izd controls the selection of mute when automute is enabled. when izd is detected mute is enabled and when izd is not detected mute is disabled. muteb pin description 0 mute dac channels 1 normal operation floating muteb becomes an output to indicate when izd occurs. l=izd detected (mute enabled), h=izd not detected (mute disabled). table 2 mute andautomute control zero pin description 0 indicates infinite zero detected from the digital input. 1 indicates infinite zero not detected from the digital input. table 3 zero pin output figure 13 shows the application and release of mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when mute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards v mid witha time constant of approximately 64 input samples. when mute is de- asserted, the output will restart almost immediately from the current input sample.
WM8728 production data w pd rev 3.1 december 2002 16 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s) figure 13 application andrelease of soft mute the muteb pin is an input to select mute or not mute. muteb is active low; taking the pin low causes the filters to soft mute, ramping down the audio signal over a few milliseconds. taking muteb high again allows data into the filter. the automute function detects a series of zero value audio samples of 1024 samples long being applied to bothchannels. after suchan event, a latchis set whose output (automuted) is wire ored through a 10kohm resistor to the muteb pin. thus if the muteb pin is not being driven, the automute function will assert mute. if muteb is tied high, automuted is overridden and will not mute unless the izd register bit is set. if muteb is driven from a bi-directional source, then both mute and automute functions are available. if muteb is not driven, automuted appears as a weak output (10kohm-source impedance) so can be used to drive external mute circuits. automuted will be removed as soon as any channel receives a non-zero input. a diagram showing how the various mute modes interact is shown below figure 14. izd (register bit) automuted (internal signal) 10k ? ? ? ? mut (register bit) softmute (internal signal) muteb pin figure 14 selection logic for mute modes
WM8728 production data w pd rev 3.1 december 2002 17 inputformatselection in hardware mode, lati2s (pin 20) and csbiwl (pin 15) become input controls for selection of input data format type and input data word length. lati2s csbiwl input data mode 00 24-bit right justified 01 20-bit right justified 10 16-bit i 2 s 11 24-bit i 2 s table 4 input format selection note: in 24 bit i 2 s mode, any width of 24 bits or less is supported provided that lrcin is high for a minimum of 24 bckins and low for a minimum of 24 bckins. if exactly 32 bckins occur in one lrcin (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. de-emphasis control in hardware mode, sdidem (pin 18) becomes an input control for selection of de-emphasis filtering to be applied. sdidem de-emphasis 0off 1on table 5 de-emphasis control software control interface the software control interface may be operated using a 2-wire interface compatible or 3-wire (spi- compatible) interface. selection of control mode the WM8728 may be programmed to operate in hardware or software control modes. this is achieved by setting the state of the mode pin. mode interface format 0 hardware control mode 1 software control mode table 6 control interface mode selection 3-wire (spi compatible) serial control mode in this mode, sdidem is used for the program data, sckdsd is used to clock in the program data and lati2s is used to latch in the program data. the 3-wire interface protocol is shown in figure 15. lati2s sckdsd sdidem b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 15 3-wire serial interface notes: 1. b[15:9] are control address bits 2. b[8:0] are control data bits 3. csbiwl needs to be low during writes C see figure 6
WM8728 production data w pd rev 3.1 december 2002 18 2-wire serial control mode in 2-wire mode, which is the default, sdidem is used for the program data and sckdsd is used to clock in the program data see figure 16. WM8728 has an address of 001101x (binary) which represents an audio device. the final address digit is dependent on pin csbiwl, which should be tied to either dvdd or dgnd. this allows the device to have a choice of two identification header addresses used in the 2 wire interface word. this feature allows more than one WM8728 device to be present on the interface bus. lati2s should be tied to either dvdd or dgnd, as it is unused. this pin if toggled from low to high and high to low, will cause the device to enter the 3-wire interface mode and cannot be placed back into 2-wire mode except by toggling the mode pin, or powering off the device. sdidem sckdsd ack r addr ack data b15-8 stop start data b7-0 r/w ack figure 16 2-wire serial interface
WM8728 production data w pd rev 3.1 december 2002 19 register map WM8728 uses a total of 4 program registers, which are 16-bits long. these registers are all loaded through input pin sdidem. using either 2-wire or 3-wire serial control mode as shown in figure 15 and figure 16. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 m0 0 0 0 0 0 0 0 updatel lat7 lat6 lat5 lat4 lat3 lat2 lat1 lat0 m1 0 0 0 0 0 0 1 updater rat7 rat6 rat5 rat4 rat3 rat2 rat1 rat0 m2 0 0 0 0 0 1 0 0 0 0 iw2 iw1 iw0 pwdn deemph mut m3 0 0 0 0 0 1 1 izd 0 0 bcp rev 0 atc lrp i 2 s address data table 7 mapping of program registers register address (a3,a2,a1,a0) bits name default description [7:0] lat[7:0] 11111111 (0db) attenuation data for left channel in 0.5db steps, see table 10 0000 dacl attenuation 8 updatel 0 attenuation data load control for left channel. 0: store dacl in intermediate latch(no change to output) 1: store dacl and update attenuation on bothchannels. [7:0] rat[7:0] 11111111 (0db) attenuation data for right channel in 0.5db steps, see table 10 0001 dacr attenuation 8 updater 0 attenuation data load control for right channel. 0: store dacr in intermediate latch(no change to output) 1: store dacr and update attenuation on bothchannels. 0mut 0 left and right dacs soft mute control. 0: no mute 1: mute 1deemph 0 de-emphasis control. 0: de-emphasis off 1: de-emphasis on 2pwdn 0 left and right dacs power-down control 0: all dacs running, output is active 1: all dacs in power saving mode, output muted 0010 dac control [5:3] iw[2:0] 0 audio data format select, see table 15 0i 2 s0 audio data format select, see table 15 1lrp 0 polarity select for lrcin/dsp mode select. 0: normal lrcin polarity/dsp late mode 1: inverted lrcin polarity/dsp early mode 2atc 0 attenuator control. 0: all dacs use attenuation as programmed. 1: right channel dacs use corresponding left dac attenuation 4rev 0 output phase reverse. 5bcp 0 bckin polarity 0 : normal bckin polarity 1: inverted bckin polarity 0011 interface control 8izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect disabled 1: infinite zero detect enabled table 8 register bit descriptions
WM8728 production data w pd rev 3.1 december 2002 20 attenuation control each dac channel can be attenuated digitally before being applied to the digital filter. attenuation is 0db by default but can be set between 0 and 127.5db in 0.5db steps using the 8 attenuation control bits. all attenuation registers are double latched allowing new values to be pre-latched to both channels before being updated synchronously. setting the update bit on any attenuation write will cause all pre-latched values to be immediately applied to the dac channels. register address bits label default description [7:0] lat[7:0] 11111111 (0db) attenuation data for left channel dacl in 0.5db steps. 0000 attenuation dacl 8 updatel 0 controls simultaneous update of all attenuation latches 0: store dacl in intermediate latch(no change to output) 1: store dacl and update attenuation on all channels. [7:0] rat[7:0] 11111111 (0db) attenuation data for right channel dacr in 0.5db steps. 0001 attenuation dacr 8 updater 0 controls simultaneous update of all attenuation latches 0: store dacr in intermediate latch(no change to output) 1: store dacr and update attenuation on all channels. table 9 attenuation register map note: 1. the update bit is not latched. if update=0, the attenuation value will be written to the pre-latch but not applied to the relevant dac. if update=1, all pre-latched values and the current value being written will be applied on the next input sample. 2. care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise. dac output attenuation registers lat and rat control the left and right channel attenuation. table 9 shows how the attenuation levels are selected from the 8-bit words. xat[7:0] attenuation level 00(hex) db (mute) 01(hex) 127.5db :: :: :: fe(hex) 0.5db ff(hex) 0db table 10 attenuation control levels mute modes setting the mut register bit will apply a 'soft' mute to the input of the digital filters: register address bit label default description 0010 dac control 0mut 0 soft mute select 0 : normal operation 1: soft mute all channels table 11 mute control
WM8728 production data w pd rev 3.1 december 2002 21 de-emphasis mode setting the deemph register bit puts the digital filters into de-emphasis mode: register address bit label default description 0010 dac control 1 deemph 0 de-emphasis mode select: 0 : de-emphasis off 1: de-emphasis on table 12 de-emphasis control powerdown mode setting the pwdn register bit immediately connects all outputs to v mid and selects a low power mode. all trace of the previous input samples is removed, and all control register settings are cleared. when pwdn is cleared again the first 16 input samples will be ignored, as the fir will repeat it's power-on initialisation sequence. register address bit label default description 0010 dac control 2pwdn 0 power down mode select: 0 : normal mode 1: power down mode table 13 powerdown control digital audio interface control registers the WM8728 has a fully featured digital audio interface that is a superset of that contained in the wm8716. interface format is selected via the iwl[2:0] register bits in register m2 and the i 2 s register bit in m3. register address bit label default description 0010 dac control 5:3 iwl[2:0] 000000 interface format select 0011 interface control 0i 2 s0 interface format select table 14 interface format controls iw2 i 2 s iw1 iw0 audio interface description (note 1) 0000 16 bit right justified mode 0001 20 bit right justified mode 0010 24 bit right justified mode 0011 24 bit left justified mode 0100 16 bit i 2 s mode 0101 24 bit i 2 s mode 0110 20 bit i 2 s mode 0111 20 bit left justified mode 1000 16 bit dsp mode 1001 20 bit dsp mode 1010 24 bit dsp mode 1011 32 bit dsp mode 1100 16 bit left justified mode table 15 audio data input format note: in all modes, the data is signed 2's complement. the digital filters always input 24-bit data. if the dac is programmed to receive 16 or 20 bit data, the WM8728 pads the unused lsbs with zeros. if the dac is programmed into 32-bit mode, the 8 lsbs are treated as zero.
WM8728 production data w pd rev 3.1 december 2002 22 selection of lrcin polarity in left justified, right justified or i 2 s modes, the lrp register bit controls the polarity of lrcin. if this bit is set high, the expected polarity of lrcin will be the opposite of that shown in figure 8, figure 9 and figure 10. note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. register address bit label default description 0011 interface control 1 lrp 0 lrcin polarity (normal) 0 : normal lrcin polarity 1: inverted lrcin polarity table 16 lrcin polarity control in dsp modes, the lrcin register bit is used to select between early and late modes (see figure 11 and figure 12. register address bit label default description 0011 interface control 1 lrp 0 dsp format (dsp modes) 0 : late dsp mode 1: early dsp mode table 17 dsp format control in dsp early mode, the first bit is sampled on the bckin rising edge following the one that detects a low to high transition on lrcin. in dsp late mode, the first bit is sampled on the bckin rising edge, which detects a low to high transition on lrcin. no bckin edges are allowed between the data words. the word order is din left, din right. attenuator control mode setting the atc register bit causes the left channel attenuation settings to be applied to both left and right channel dacs from the next audio input sample. no update to the attenuation registers is required for atc to take effect. register address bit label default description 0011 interface control 2 atc 0 attenuator control mode: 0 : right channels use right attenuation 1: right channels use left attenuation table 18 attenuation control select output phase reversal the rev register bit controls the phase of the output signal. setting the rev bit causes the phase of the output signal to be inverted. register address bit label default description 0011 interface control 4 rev 0 analogue output phase 0: normal 1: inverted table 19 output phase control bckin polarity by default, lrcin and din are sampled on the rising edge of bckin and should ideally change on the falling edge. data sources which change lrcin and din on the rising edge of bckin can be supported by setting the bcp register bit. setting bcp to 1 inverts the polarity of bckin to the inverse of that shown in figure 8, figure 9, figure 10, figure 11 and figure 12. register address bit label default description 0011 interface control 5 bcp 0 bckin polarity 0 : normal bckin polarity 1: inverted bckin polarity table 20 bckin polarity control
WM8728 production data w pd rev 3.1 december 2002 23 infinite zero detection setting the izd register bit determines whether the device is automuted when a sequence of more than 1024 zeros is detected. register address bit label default description 0011 interface control 8izd 0 infinite zero detection circuit control and automute control 0: infinite zero detect disabled 1: infinite zero detect enabled table 21 izd control digital filter characteristics parameter symbol test conditions min typ max unit passband edge -3db 0.487fs passband ripple f < 0.444fs 0.05 db stopband attenuation f > 0.555fs -60 db table 22 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 17 dac digital filter frequency response -44.1, 48 and96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 18 dac digital filter ripple -44.1, 48 and96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 19 dac digital filter frequency response -192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 20 dac digital filter ripple -192khz
WM8728 production data w pd rev 3.1 december 2002 24 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 21 de-emphasis frequency response (32khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 22 de-emphasis error (32khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 23 de-emphasis frequency response (44.1khz) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5 10 15 20 response (db) frequency (khz) figure 24 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) figure 25 de-emphasis frequency response (48khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 26 de-emphasis error (48khz)
WM8728 production data w pd rev 3.1 december 2002 25 dsd mode characteristics -60 -50 -40 -30 -20 -10 0 0 500 1000 1500 2000 response (db) frequency (khz) figure 27 dsd frequency response - no post filter -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 50 100 150 200 250 300 350 400 response (db) frequency (khz) figure 28 dsd frequency response - no post filter -120 -100 -80 -60 -40 -20 0 0 50 100 150 200 250 300 350 400 response (db) frequency (khz) figure 29 dsd frequency response - 4th order post filter -8 -6 -4 -2 0 0 10 20 30 40 50 60 response (db) frequency (khz) figure 30 dsd frequency response - 4th order post filter
WM8728 production data w pd rev 3.1 december 2002 26 applications information recommended external components (pcm audio) 20 dvdd dgnd lati2s agnd avdd 7 6 software i/f or hardware control WM8728 notes: 1. agnd and dgnd should be connected as close to the WM8728 as possible. 2. c 2 ,c 3 ,c 4 and c 8 should be positioned as close to the WM8728 as possible. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. vrefp vrefn c 3 c 4 c 5 c 2 dvdd c 1 19 sckdsd 18 sdidem voutr 11 c 6 voutl c 7 ac-coupled voutr/l to external lpf 16 mode 17 muteb 8 avdd 4 mclk 3 bckin 2 din audio serial data i/f dgnd agnd 1 lrcin 10 14 9 13 + + + + software/hardware control mode select 15 csbiwl 5 zero dvdd r1 agnd 12 vmid c 9 c 8 + figure 31 external components diagram recommended external components values component reference suggested value description c1 and c5 10 f de-coupling for dvdd and avdd/vrefp c2 to c4 0.1 f de-coupling for dvdd and avdd/vrefp c6 and c7 10 f output ac coupling caps to remove midrail dc level from outputs. c8 0.1 f c9 10 f reference de-coupling capacitors for vmid pin. r1 10k ? 10k pull-up to dvdd table 23 external components description
WM8728 production data w pd rev 3.1 december 2002 27 recommended external components (dsd audio) 20 dvdd dgnd lati2s agnd avdd 7 6 mute control WM8728 notes: 1. agnd and dgnd should be connected as close to the WM8728 as possible. 2. c 2 ,c 3 ,c 4 and c 8 should be positioned as close to the WM8728 as possible. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. 4. when using monophase dsd encoding pin 3 bckin should be tied to dvdd. in biphase dsd encoding bckin runs at 2 cycles per bit. vrefp vrefn c 3 c 4 c 5 c 2 dvdd c 1 19 sckdsd 18 sdidem voutr 11 c 6 voutl c 7 ac-coupled voutr/l to external lpf 16 mode 17 muteb 8 avdd 4 mclk 3 bckin 2 din dsd right bitstream dgnd agnd 1 lrcin 10 14 9 13 + + + + 15 csbiwl dgnd dvdd dsd left bitstream dsd bit clock dsd biphase mode clock dvdd r1 5 zero vmid c 9 c 8 agnd 12 + figure 32 external connections for dsd applications recommended external components values for dsd component reference suggested value description c1 and c5 10 f de-coupling for dvdd and avdd. c2 to c4 0.1 f de-coupling for dvdd and avdd. c6 and c7 10 f output ac coupling caps to remove midrail dc level from outputs. c8 0.1 f c9 10 f reference de-coupling capacitors for vmid pin. r1 10k ? 10k pull-up to dvdd table 24 external components for dsd
WM8728 production data w pd rev 3.1 december 2002 28 recommended dsd connections cxd2751q WM8728eds bcka dsar dsal mclk din lrcin 64fs right channel data left channel data figure 33 monophase mode connection diagram cxd2751q WM8728eds bcka bckd dsar dsal mclk din lrcin 64fs bckin 128fs right channel data left channel data figure 34 biphase mode connection diagram ? dsd mode is selected with the WM8728 by pulling the sckdsd pin high while the mode pin is held low. ? dsd mode is hardware only operation. ? the cxd2751q from sony is a signal processor for super audio cd playback. recommended analogue low pass filter for pcm data format (optional) + _ + +vs -vs 10uf 51 ? 7.5k ? 680pf 1.8k ? 47k ? 4.7k ? 4.7k ? 1.0nf figure 35 recommended low pass filter (optional)
WM8728 production data w pd rev 3.1 december 2002 29 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.b ds:20pinssop (7.2x5.3x1.75mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 0.125 ref c l gauge plane 0.25 l 1
WM8728 production data w pd rev 3.1 december 2002 30 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated withcustomer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information withalteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any suchuse. resale of wms products or services withstatements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any suchuse. address: wolfson microelectronics plc 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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